The Communication Technologies Division at CTTC is currently accepting applications for one researcher position in the Communication Technologies Division – PHYCOM Department. The position is available for International students.
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC), in Castelldefels – Barcelona, is a growing and well-funded research institution fostering excellence and diversity. CTTC offers a highly international environment at an exceptionally attractive location. As a research centre in telecommunications and geomatic technologies, CTTC provides a fertile environment for research cooperation and innovation between different disciplines.
The candidate must have fluency in English (spoken and written) and advanced communication skills.
- Applications Deadline: January 26, 2021
- Course Level: Position is available to pursue research.
- Study Subject: Position is awarded in the fields of Communication Technologies Division – PHYCOM Department.
- Scholarship Award: The position is temporary, with a perspective to become permanent. A competitive salary will be determined according to qualifications, work experience and budget availability. CTTC is particularly interested in candidates with a good balance of academic qualifications and know-how in their field of knowledge.
- Nationality: Position is available for International students.
- Number of Scholarships: One research position is available.
- Scholarship can be taken in Spain
Eligibility for the Scholarship
Eligible Countries: Position is available for International students.
Entrance Requirements: Applicants must meet the following criteria:
The applicant is expected to:
- Be a proactive team player
- Carry out innovative applied research
- Have project management skills
- Lead or participate in the preparation of competitive funding project proposals
- Lead or participate in dissemination activities
Qualifications and Experience
We are looking for a highly motivated and enthusiastic researcher/engineer with solid research, analytical, problem-solving and the programming skills quoted below. The candidate must have fluency in English (spoken and written) and advanced communication skills. Previous experience in fields related to the specific position will be considered a clear plus for the candidate.
- At least 5 years’ experience in DSP algorithm modelling using Matlab.
- Excellent FPGA algorithm development skills using VHDL or Verilog HDL languages with special emphasis on advanced RTL coding skills to guarantee timing closure in dense and/or high-speed HDL designs. Priority will be given to candidates with a solid FPGA implementation portfolio of DSP algorithms. Expert knowledge of the Xilinx Vivado Design Suite is a must.
- At least 5 years’ experience in firmware development with C or C++, Linux shell scripting, Python and HDL languages, using debugging and profiling tools (e.g., gdb, perf) and version control systems (Git) and IDEs.
- The applicants must have a deep understanding of OS architecture (Linux or other UNIX-like OS), a strong background on embedded systems, Linux kernel space and user space programming, RTOS and real-time programming techniques, be familiar with the modern ARM 32 and 64-bit architecture and GNU compiler tool chain. The candidate must also possess strong experience in HW-SW co-design practices applied to FPGA-based SoC devices.
- Hands-on knowledge or previous exposure to wireless communications standards, digital signal processing techniques and SDR.
- Experience in participating in the entire development cycle: from system conception and specifications, through high-level modelling, FPGA development, real-time testing, debugging and lab-based performance validation of the developed algorithm or (sub-) system.
- Outstanding oral and writing English skills.
- Effective verbal and written communication skills and ability to work in an international team.
- Hands-on experience on Xilinx Partial Configuration design cycle will be considered a valuable asset.
- It will be highly appreciated having design experience with specific SDR platforms where FPGA devices are used as DSP co-processors e.g., Ettus USRP X and E series platforms, Xilinx ZC706/ZCU102 boards combined with the AD-FMCOMMS2/3 SDR RF front-end.
- Prior research experience in academia or industry
- Career distinctions
- Experience in leading and/or participating in the preparation of scientific publications.
- Experience in preparation of EC funded research grant proposals.
- Experience from participating in national and international research projects with partners from academia and industry.
English Language Requirements: The candidate must have fluency in English (spoken and written) and advanced communication skills.
How to Apply: Applications should include:
- Full CV including name (email address, etc.) of three referees.
- Scanned copies of all the obtained degree titles (e.g., originals of the B.Sc., M.Sc. and PhD titles). When a title is expected to be obtained in a short timeframe (e.g., PhD degree), the candidate should provide a letter signed by his/her University supervisor indicating the estimated examination/graduation date.
- Cover letter stating the motivation and suitability of the candidate.
The documents should be sent in PDF format through this online application. Applications for the position received by email will not be taken into consideration. CVs and any other data gathered during this process will be handled confidentially.